USBHS_DEVISR

Device Global Interrupt Status Register

  0x0004 32 Read-only 0x00000000  
Parent topic: Register Summary

Device Global Interrupt Status Register

Bit  31 30 29 28 27 26 25 24  
  DMA_6 DMA_5 DMA_4 DMA_3 DMA_2 DMA_1 DMA_0    
Access                   
Reset  0 0 0 0 0 0 0    
Bit  23 22 21 20 19 18 17 16  
      PEP_9 PEP_8 PEP_7 PEP_6 PEP_5 PEP_4  
Access                   
Reset      0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
  PEP_3 PEP_2 PEP_1 PEP_0          
Access                   
Reset  0 0 0 0          
Bit  7 6 5 4 3 2 1 0  
    UPRSM EORSM WAKEUP EORST SOF MSOF SUSP  
Access                   
Reset    0 0 0 0 0 0 0  

Bit 0 – SUSP: Suspend Interrupt

Suspend Interrupt

ValueDescription
0

Cleared when the USBHS_DEVICR.SUSPC bit is written to one to acknowledge the interrupt, or when the Wakeup (WAKEUP) interrupt bit is set.
1

Set when a USB “Suspend” idle bus state has been detected for 3 frame periods (J state for 3 ms). This triggers a USB interrupt if USBHS_DEVIMR.SUSPE = 1.

Bit 1 – MSOF: Micro Start of Frame Interrupt

Micro Start of Frame Interrupt

ValueDescription
0

Cleared when the USBHS_DEVICR.MSOFC bit is written to one to acknowledge the interrupt.
1

Set in High-speed mode when a USB “Micro Start of Frame” PID (SOF) has been detected (every 125 μs). This triggers a USB interrupt if MSOFE = 1. The MFNUM field is updated. The FNUM field is unchanged.

Bit 2 – SOF: Start of Frame Interrupt

Start of Frame Interrupt

ValueDescription
0

Cleared when the USBHS_DEVICR.SOFC bit is written to one to acknowledge the interrupt.
1

Set when a USB “Start of Frame” PID (SOF) has been detected (every 1 ms). This triggers a USB interrupt if SOFE = 1. The FNUM field is updated. In High-speed mode, the MFNUM field is cleared.

Bit 3 – EORST: End of Reset Interrupt

End of Reset Interrupt

ValueDescription
0

Cleared when the USBHS_DEVICR.EORSTC bit is written to one to acknowledge the interrupt.
1

Set when a USB “End of Reset” has been detected. This triggers a USB interrupt if USBHS_DEVIMR.EORSTE = 1.

Bit 4 – WAKEUP: Wakeup Interrupt

Wakeup Interrupt

This interrupt is generated even if the clock is frozen by the USBHS_CTRL.FRZCLK bit.

ValueDescription
0

Cleared when the USBHS_DEVICR.WAKEUPC bit is written to one to acknowledge the interrupt (USB clock inputs must be enabled before), or when the Suspend (SUSP) interrupt bit is set.
1

Set when the USBHS is reactivated by a filtered non-idle signal from the lines (not by an upstream resume). This triggers an interrupt if USBHS_DEVIMR.WAKEUPE = 1.

Bit 5 – EORSM: End of Resume Interrupt

End of Resume Interrupt

ValueDescription
0

Cleared when the USBHS_DEVICR.EORSMC bit is written to one to acknowledge the interrupt.
1

Set when the USBHS detects a valid “End of Resume” signal initiated by the host. This triggers a USB interrupt if USBHS_DEVIMR.EORSME = 1.

Bit 6 – UPRSM: Upstream Resume Interrupt

Upstream Resume Interrupt

ValueDescription
0

Cleared when the USBHS_DEVICR.UPRSMC bit is written to one to acknowledge the interrupt (USB clock inputs must be enabled before).
1

Set when the USBHS sends a resume signal called “Upstream Resume”. This triggers a USB interrupt if USBHS_DEVIMR.UPRSME = 1.

Bits 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 – PEP_: Endpoint x Interrupt

Endpoint x Interrupt

ValueDescription
0

Cleared when the interrupt source is serviced.
1

Set when an interrupt is triggered by endpoint x (USBHS_DEVEPTISRx, USBHS_DEVEPTIMRx). This triggers a USB interrupt if USBHS_DEVIMR.PEP_x = 1.

Bits 25, 26, 27, 28, 29, 30, 31 – DMA_: DMA Channel x Interrupt

DMA Channel x Interrupt

ValueDescription
0

Cleared when the USBHS_DEVDMASTATUSx interrupt source is cleared.
1

Set when an interrupt is triggered by the DMA channel x. This triggers a USB interrupt if DMA_x = 1.