USBHS_DEVDMANXTDSCx

Device DMA Channel x Next Descriptor Address Register

  0x0300 + (x-1)*0x10 [x=1..7] 32 Read/Write 0   7 16 1index -1
Parent topic: Register Summary

Device DMA Channel x Next Descriptor Address Register

Bit  31 30 29 28 27 26 25 24  
  NXT_DSC_ADD[31:24]  
Access                   
Reset  0 0 0 0 0 0 0 0  
Bit  23 22 21 20 19 18 17 16  
  NXT_DSC_ADD[23:16]  
Access                   
Reset  0 0 0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
  NXT_DSC_ADD[15:8]  
Access                   
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  NXT_DSC_ADD[7:0]  
Access                   
Reset  0 0 0 0 0 0 0 0  

Bits 31:0 – NXT_DSC_ADD[31:0]: Next Descriptor Address

Next Descriptor Address

This field points to the next channel descriptor to be processed. This channel descriptor must be aligned, so bits 0 to 3 of the address must be equal to zero.