GMAC_SATx

GMAC Specific Address n Top Register

The addresses stored in the Specific Address Registers are deactivated at reset or when their corresponding Specific Address Register Bottom is written. They are activated when Specific Address Register Top is written.

  0x8C + (x-1)*0x08 [x=1..4] 32 Read/Write 0x00000000   4 8 1index -1
Parent topic: Register Summary

GMAC Specific Address n Top Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
  ADDR[15:8]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  ADDR[7:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 15:0 – ADDR[15:0]: Specific Address n

Specific Address n

The most significant bits of the destination address, that is, bits 47:32.