SDRAMC OCMS KEY1 Register
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
KEY1[31:24] | |||||||||
Access | W | W | W | W | W | W | W | W | |
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
KEY1[23:16] | |||||||||
Access | W | W | W | W | W | W | W | W | |
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
KEY1[15:8] | |||||||||
Access | W | W | W | W | W | W | W | W | |
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
KEY1[7:0] | |||||||||
Access | W | W | W | W | W | W | W | W | |
Reset |
Off-chip Memory Scrambling (OCMS) Key Part 1
When off-chip memory scrambling is enabled, the data scrambling depends on KEY1 and KEY2 values.