UART_IMR

UART Interrupt Mask Register

The following configuration values are valid for all listed bit names of this register:

0: The corresponding interrupt is disabled.

1: The corresponding interrupt is enabled.

  0x10 32 Read-only 0x00000000  

UART Interrupt Mask Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
  CMP           TXEMPTY    
Access  R           R    
Reset  0           0    
Bit  7 6 5 4 3 2 1 0  
  PARE FRAME OVRE       TXRDY RXRDY  
Access  R R R       R R  
Reset  0 0 0       0 0  

Bit 0 – RXRDY: Mask RXRDY Interrupt

Mask RXRDY Interrupt

Bit 1 – TXRDY: Disable TXRDY Interrupt

Disable TXRDY Interrupt

Bit 5 – OVRE: Mask Overrun Error Interrupt

Mask Overrun Error Interrupt

Bit 6 – FRAME: Mask Framing Error Interrupt

Mask Framing Error Interrupt

Bit 7 – PARE: Mask Parity Error Interrupt

Mask Parity Error Interrupt

Bit 9 – TXEMPTY: Mask TXEMPTY Interrupt

Mask TXEMPTY Interrupt

Bit 15 – CMP: Mask Comparison Interrupt

Mask Comparison Interrupt