Host General Control Register
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SPDCONF[1:0] | RESUME | RESET | SOFE | ||||||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |
Start of Frame Generation Enable
This bit is set when a USB reset is requested or an upstream resume interrupt is detected (USBHS_HSTISR.TXRSMI).
| Value | Description |
|---|---|
| 0 | Disables the SOF generation and leaves the USB bus in idle state. |
| 1 | Generates SOF on the USB bus in Full- or High-speed mode and sends “keep alive” signals in Low-speed mode. |
Send USB Reset
This bit is cleared when the USB Reset has been sent.
It may be useful to write a zero to this bit when a device disconnection is detected (USBHS_HSTISR.DDISCI = 1) whereas a USB Reset is being sent.
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Generates a USB Reset on the USB bus. |
Send USB Resume
This bit is cleared when the USB Resume has been sent or when a USB reset is requested.
This bit should be written to one only when the start of frame generation is enabled (SOFE = 1).
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Generates a USB Resume on the USB bus. |
Mode Configuration
This field contains the host speed capability:.
| Value | Name | Description |
|---|---|---|
| 0 | NORMAL | The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. |
| 1 | LOW_POWER | For a better consumption, if high speed is not needed. |
| 2 | HIGH_SPEED | Forced high speed. |
| 3 | FORCED_FS | The host remains in Full-speed mode whatever the peripheral speed capability. |