PWM_IER1

PWM Interrupt Enable Register 1

This register can only be written if bits WPSWS1 and WPHWS1 are cleared in the PWM Write Protection Status Register.

  0x10 32 Write-only –  
Parent topic: Register Summary

PWM Interrupt Enable Register 1

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
          FCHID3 FCHID2 FCHID1 FCHID0  
Access          W W W W  
Reset          0 0 0 –  
Bit  15 14 13 12 11 10 9 8  
                   
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
          CHID3 CHID2 CHID1 CHID0  
Access          W W W W  
Reset          0 0 0 –  

Bits 0, 1, 2, 3 – CHIDx: Counter Event on Channel x Interrupt Enable

Counter Event on Channel x Interrupt Enable

Bits 16, 17, 18, 19 – FCHIDx: Fault Protection Trigger on Channel x Interrupt Enable

Fault Protection Trigger on Channel x Interrupt Enable