Free-running mode is enabled by clearing DACC_TRIGR.TRGENx and DACC_MR.MAXSx.
The conversion starts as soon as at least one channel is enabled. Once data is written in the DACC Conversion Data Register (DACC_CDRx), 12 DAC clock periods later, the converted data is available at the corresponding analog output. The next data is converted only when the EOC of the previous data is set.
If the FIFO is emptied, no conversion occurs and the data is maintained at the output of the DAC.
Figure 1. Conversion Sequence in Free-running Mode
