SPI_RDR

SPI Receive Data Register

  0x08 32 Read-only 0x0  

SPI Receive Data Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
          PCS[3:0]  
Access          R R R R  
Reset          0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
  RD[15:8]  
Access  R R R R R R R R  
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  RD[7:0]  
Access  R R R R R R R R  
Reset  0 0 0 0 0 0 0 0  

Bits 15:0 – RD[15:0]: Receive Data

Receive Data

Data received by the SPI Interface is stored in this register in a right-justified format. Unused bits are read as zero.

Bits 19:16 – PCS[3:0]: Peripheral Chip Select

Peripheral Chip Select

In Master mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits are read as zero.

When using Variable Peripheral Select mode (PS = 1 in SPI_MR), it is mandatory to set SPI_MR.WDRBT bit if the PCS field must be processed in SPI_RDR.