USBHS_DEVEPTIDRx (ISOENPT)

Device Endpoint Interrupt Disable Register (Isochronous Endpoints)

This register view is relevant only if EPTYPE = 0x1 in ”Device Endpoint x Configuration Register”.

For additional information, see ”Device Endpoint x Mask Register (Isochronous Endpoints)”.

This register always reads as zero.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Clears the corresponding bit in USBHS_DEVEPTIMRx.

  0x0220 + x*0x04 [x=0..9] 32 Read/Write 0   10 4 x

Device Endpoint Interrupt Disable Register (Isochronous Endpoints)

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                EPDISHDMAC  
Access                   
Reset                0  
Bit  15 14 13 12 11 10 9 8  
    FIFOCONC   NBUSYBKEC   ERRORTRANSEC DATAXEC MDATEC  
Access                   
Reset    0   0   0 0 0  
Bit  7 6 5 4 3 2 1 0  
  SHORTPACKETEC CRCERREC OVERFEC HBISOFLUSHEC HBISOINERREC UNDERFEC RXOUTEC TXINEC  
Access                   
Reset  0 0 0 0 0 0 0 0  

Bit 0 – TXINEC: Transmitted IN Interrupt Clear

Transmitted IN Interrupt Clear

Bit 1 – RXOUTEC: Received OUT Data Interrupt Clear

Received OUT Data Interrupt Clear

Bit 2 – UNDERFEC: Underflow Interrupt Clear

Underflow Interrupt Clear

Bit 3 – HBISOINERREC: High Bandwidth Isochronous IN Error Interrupt Clear

High Bandwidth Isochronous IN Error Interrupt Clear

Bit 4 – HBISOFLUSHEC: High Bandwidth Isochronous IN Flush Interrupt Clear

High Bandwidth Isochronous IN Flush Interrupt Clear

Bit 5 – OVERFEC: Overflow Interrupt Clear

Overflow Interrupt Clear

Bit 6 – CRCERREC: CRC Error Interrupt Clear

CRC Error Interrupt Clear

Bit 7 – SHORTPACKETEC: Shortpacket Interrupt Clear

Shortpacket Interrupt Clear

Bit 8 – MDATEC: MData Interrupt Clear

MData Interrupt Clear

Bit 9 – DATAXEC: DataX Interrupt Clear

DataX Interrupt Clear

Bit 10 – ERRORTRANSEC: Transaction Error Interrupt Clear

Transaction Error Interrupt Clear

Bit 12 – NBUSYBKEC: Number of Busy Banks Interrupt Clear

Number of Busy Banks Interrupt Clear

Bit 14 – FIFOCONC: FIFO Control Clear

FIFO Control Clear

Bit 16 – EPDISHDMAC: Endpoint Interrupts Disable HDMA Request Clear

Endpoint Interrupts Disable HDMA Request Clear