The MATRIX manages the masters listed in he following table. Each master can perform an access to an available slave concurrently with other masters. lists the available masters.
Each master has its own specifically-defined decoder. To simplify addressing, all the masters have the same decodings.
Master Index | Name |
---|---|
0 | Cortex-M7 |
1 | Cortex-M7 |
2 | Cortex-M7 Peripheral Port |
3 | Integrated Check Monitor |
4, 5 | XDMAC |
6 | ISI DMA |
7 | Media LB |
8 | USB DMA |
9 | Ethernet MAC DMA |
10 | CAN0 DMA |
11 | CAN1 DMA |
12 | Cortex-M7 |