The following table provides valid paths for master to slave accesses. The paths shown as “-” are forbidden or not wired.
Masters | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Slaves | Cortex-M7 | Cortex-M7 | Cortex-M7 Peripheral Port | ICM | Central DMA IF0 | Central DMA IF1 | ISI DMA |
MediaLB DMA |
USB DMA |
GMAC DMA |
CAN0 DMA |
CAN1 DMA |
Cortex-M7 | |
0 | Internal SRAM | – | – | – | X | X | – | – | – | – | – | – | – | – |
1 | Internal SRAM | – | – | – | – | – | X | X |
X |
X |
X |
X |
X |
– |
2 | Internal ROM | X | – | – | – | – | – | – | – | – | – | – | – | – |
3 | Internal Flash | X | – | – | X | – | X | – | – | X |
X |
– | – | – |
4 | USB HS Dual Port RAM | – | X | – | – | – | – | – | – | – | – | – | – | – |
5 | External Bus Interface | – | X | – | X | X | X | X |
X |
X |
X |
X |
X |
– |
6 | QSPI | – | – | – | X | – | X | – | – | X |
X |
– | – | X |
7 | Peripheral Bridge | – | X | X | – | – | X | – | – | – | – | – | – | – |
8 | Cortex-M7 AHB Slave (AHBS) (see Note) | – | – | – | X | X | – | X |
X |
X |
X |
X |
X |
– |