SSC_CR

SSC Control Register

  0x0 32 Write-only –  
Parent topic: Register Summary

SSC Control Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
  SWRST           TXDIS TXEN  
Access  W           W W  
Reset  –           – –  
Bit  7 6 5 4 3 2 1 0  
              RXDIS RXEN  
Access              W W  
Reset              – –  

Bit 0 – RXEN: Receive Enable

Receive Enable

ValueDescription
0

No effect.
1

Enables Receive if RXDIS is not set.

Bit 1 – RXDIS: Receive Disable

Receive Disable

ValueDescription
0

No effect.
1

Disables Receive. If a character is currently being received, disables at end of current character reception.

Bit 8 – TXEN: Transmit Enable

Transmit Enable

ValueDescription
0

No effect.
1

Enables Transmit if TXDIS is not set.

Bit 9 – TXDIS: Transmit Disable

Transmit Disable

ValueDescription
0

No effect.
1

Disables Transmit. If a character is currently being transmitted, disables at end of current character transmission.

Bit 15 – SWRST: Software Reset

Software Reset

ValueDescription
0

No effect.
1

Performs a software reset. Has priority on any other bit in SSC_CR.