SDRAMC Configuration Register
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
TXSR[3:0] | TRAS[3:0] | ||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
TRCD[3:0] | TRP[3:0] | ||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
TRC_TRFC[3:0] | TWR[3:0] | ||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
DBW | CAS[1:0] | NB | NR[1:0] | NC[1:0] | |||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
Number of Column Bits
Reset value is 8 column bits.
Value | Name | Description |
---|---|---|
0 | COL8 |
8 bits to define the column number, up to 256 columns. |
1 | COL9 |
9 bits to define the column number, up to 512 columns. |
2 | COL10 |
10 bits to define the column number, up to 1024 columns. |
3 | COL11 |
11 bits to define the column number, up to 2048 columns. |
Number of Row Bits
Reset value is 11 row bits.
Value | Name | Description |
---|---|---|
0 | ROW11 |
11 bits to define the row number, up to 2048 rows |
1 | ROW12 |
12 bits to define the row number, up to 4096 rows |
2 | ROW13 |
13 bits to define the row number, up to 8192 rows |
3 |
Reserved |
Number of Banks
Reset value is two banks.
Value | Name | Description |
---|---|---|
0 | BANK2 |
2 banks |
1 | BANK4 |
4 banks |
CAS Latency
Reset value is two cycles. In the SDRAMC, only a CAS latency of two and three cycles is managed.
Value | Name | Description |
---|---|---|
0 | Reserved |
– |
1 | LATENCY1 |
1 cycle latency |
2 | LATENCY2 |
2 cycle latency |
3 | LATENCY3 |
3 cycle latency |
Data Bus Width
Reset value is 16 bits.
This bit defines the Data Bus Width, which is 16 bits. It must be set to 1.
Value | Description |
---|---|
0 |
Data bus width is 32 bits. |
1 |
Data bus width is 16 bits. |
Write Recovery Delay
Reset value is two cycles.
This field defines the Write Recovery Time in number of cycles. Number of cycles is between 0 and 15.
Row Cycle Delay and Row Refresh Cycle
Reset value is seven cycles.
This field defines two timings:
The number of cycles is between 0 and 15. The end user must program max {tRC, tRFC}.
Row Precharge Delay
Reset value is three cycles.
This field defines the delay between a Precharge Command and another Command in number of cycles. Number of cycles is between 0 and 15.
Row to Column Delay
Reset value is two cycles.
This field defines the delay between an Activate Command and a Read/Write Command in number of cycles. Number of cycles is between 0 and 15.
Active to Precharge Delay
Reset value is five cycles.
This field defines the delay between an Activate Command and a Precharge Command in number of cycles. Number of cycles is between 0 and 15.
Exit Self-Refresh to Active Delay
Reset value is eight cycles.
This field defines the delay between SCKE set high and an Activate Command in number of cycles. Number of cycles is between 0 and 15.