TC_SRx

TC Interrupt Status Register

  0x20 + x*0x40 [x=0..2] 32 Read-only 0x00000000   3 64 -1
Parent topic: Register Summary

TC Interrupt Status Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
            MTIOB MTIOA CLKSTA  
Access            R R R  
Reset            0 0 0  
Bit  15 14 13 12 11 10 9 8  
                   
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
  ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS  
Access  R R R R R R R R  
Reset  0 0 0 0 0 0 0 0  

Bit 0 – COVFS: Counter Overflow Status (cleared on read)

Counter Overflow Status (cleared on read)

ValueDescription
0

No counter overflow has occurred since the last read of the Status Register.
1

A counter overflow has occurred since the last read of the Status Register.

Bit 1 – LOVRS: Load Overrun Status (cleared on read)

Load Overrun Status (cleared on read)

ValueDescription
0

Load overrun has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 1.
1

RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Status Register, if TC_CMRx.WAVE = 0.

Bit 2 – CPAS: RA Compare Status (cleared on read)

RA Compare Status (cleared on read)

ValueDescription
0

RA Compare has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 0.
1

RA Compare has occurred since the last read of the Status Register, if TC_CMRx.WAVE = 1.

Bit 3 – CPBS: RB Compare Status (cleared on read)

RB Compare Status (cleared on read)

ValueDescription
0

RB Compare has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 0.
1

RB Compare has occurred since the last read of the Status Register, if TC_CMRx.WAVE = 1.

Bit 4 – CPCS: RC Compare Status (cleared on read)

RC Compare Status (cleared on read)

ValueDescription
0

RC Compare has not occurred since the last read of the Status Register.
1

RC Compare has occurred since the last read of the Status Register.

Bit 5 – LDRAS: RA Loading Status (cleared on read)

RA Loading Status (cleared on read)

ValueDescription
0

RA Load has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 1.
1

RA Load has occurred since the last read of the Status Register, if TC_CMRx.WAVE = 0.

Bit 6 – LDRBS: RB Loading Status (cleared on read)

RB Loading Status (cleared on read)

ValueDescription
0

RB Load has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 1.
1

RB Load has occurred since the last read of the Status Register, if TC_CMRx.WAVE = 0.

Bit 7 – ETRGS: External Trigger Status (cleared on read)

External Trigger Status (cleared on read)

ValueDescription
0

External trigger has not occurred since the last read of the Status Register.
1

External trigger has occurred since the last read of the Status Register.

Bit 16 – CLKSTA: Clock Enabling Status

Clock Enabling Status

ValueDescription
0

Clock is disabled.
1

Clock is enabled.

Bit 17 – MTIOA: TIOAx Mirror

TIOAx Mirror

ValueDescription
0

TIOAx is low. If TC_CMRx.WAVE = 0, TIOAx pin is low. If TC_CMRx.WAVE = 1, TIOAx is driven low.
1

TIOAx is high. If TC_CMRx.WAVE = 0, TIOAx pin is high. If TC_CMRx.WAVE = 1, TIOAx is driven high.

Bit 18 – MTIOB: TIOBx Mirror

TIOBx Mirror

ValueDescription
0

TIOBx is low. If TC_CMRx.WAVE = 0, TIOBx pin is low. If TC_CMRx.WAVE = 1, TIOBx is driven low.
1

TIOBx is high. If TC_CMRx.WAVE = 0, TIOBx pin is high. If TC_CMRx.WAVE = 1, TIOBx is driven high.