UART_BRGR

UART Baud Rate Generator Register

  0x20 32 Read/Write 0x00000000  
Parent topic: Register Summary

UART Baud Rate Generator Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
  CD[15:8]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  CD[7:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 15:0 – CD[15:0]: Clock Divisor

Clock Divisor

ValueDescription
0

Baud rate clock is disabled
1 to 65,535

If BRSRCCK = 0:

CD=fperipheral clock16×Baud Rate 

If BRSRCCK = 1:

CD=fPCKx16×Baud Rate