I2SC Interrupt Enable Register
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
TXUR | TXRDY | RXOR | RXRDY | ||||||
Access | W | W | W | W | |||||
Reset | – | – | – | – |
Receiver Ready Interrupt Enable
Value | Description |
---|---|
0 | Writing a ’0’ to this bit has no effect. |
1 | Writing a ’1’ to this bit sets the corresponding bit in I2SC_IMR. |
Receiver Overrun Interrupt Enable
Value | Description |
---|---|
0 | Writing a ’0’ to this bit has no effect. |
1 | Writing a ’1’ to this bit sets the corresponding bit in I2SC_IMR. |
Transmit Ready Interrupt Enable
Value | Description |
---|---|
0 | Writing a ’0’ to this bit as no effect. |
1 | Writing a ’1’ to this bit sets the corresponding bit in I2SC_IMR. |
Transmit Underflow Interrupt Enable
Value | Description |
---|---|
0 | Writing a ’0’ to this bit has no effect. |
1 | Writing a ’1’ to this bit sets the corresponding bit in I2SC_IMR. |