ICM Interrupt Status Register
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| URAD | |||||||||
| Access | R | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| RSU[3:0] | REC[3:0] | ||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RWC[3:0] | RBE[3:0] | ||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RDM[3:0] | RHC[3:0] | ||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Region Hash Completed
When RHC[i] is set, it indicates that the ICM has completed the region with identifier i.
Region Digest Mismatch
When RDM[i] is set, it indicates that there is a digest comparison mismatch between the hash value of the region with identifier i and the reference value located in the Hash Area.
Region Bus Error
When RBE[i] is set, it indicates that a bus error has been detected while hashing memory region i.
Region Wrap Condition Detected
When RWC[i] is set, it indicates that a wrap condition has been detected.
Region End Bit Condition Detected
When REC[i] is set, it indicates that an end bit condition has been detected.
Region Status Updated Detected
When RSU[i] is set, it indicates that a region status updated condition has been detected.
Undefined Register Access Detection Status
The URAD bit is only reset by the SWRST bit in ICM_CTRL.
The URAT field in ICM_UASR indicates the unspecified access type.
| Value | Description |
|---|---|
| 0 | No undefined register access has been detected since the last SWRST. |
| 1 | At least one undefined register access has been detected since the last SWRST. |