TC_CCRx

TC Channel Control Register

  0x00 + x*0x40 [x=0..2] 32 Write-only –   3 64 -1
Parent topic: Register Summary

TC Channel Control Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
                   
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
            SWTRG CLKDIS CLKEN  
Access            W W W  
Reset            – – –  

Bit 0 – CLKEN: Counter Clock Enable Command

Counter Clock Enable Command

ValueDescription
0 No effect.
1 Enables the clock if CLKDIS is not 1.

Bit 1 – CLKDIS: Counter Clock Disable Command

Counter Clock Disable Command

ValueDescription
0 No effect.
1 Disables the clock.

Bit 2 – SWTRG: Software Trigger Command

Software Trigger Command

ValueDescription
0 No effect.
1 A software trigger is performed: the counter is reset and the clock is started.