USBHS_DEVIDR

Device Global Interrupt Disable Register

This register always reads as zero.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Clears the corresponding bit in USBHS_DEVIMR.

  0x0014 32 Write-only    
Parent topic: Register Summary

Device Global Interrupt Disable Register

Bit  31 30 29 28 27 26 25 24  
  DMA_6 DMA_5 DMA_4 DMA_3 DMA_2 DMA_1 DMA_0    
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
      PEP_9 PEP_8 PEP_7 PEP_6 PEP_5 PEP_4  
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
  PEP_3 PEP_2 PEP_1 PEP_0          
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
    UPRSMEC EORSMEC WAKEUPEC EORSTEC SOFEC MSOFEC SUSPEC  
Access                   
Reset                   

Bit 0 – SUSPEC: Suspend Interrupt Disable

Suspend Interrupt Disable

Bit 1 – MSOFEC: Micro Start of Frame Interrupt Disable

Micro Start of Frame Interrupt Disable

Bit 2 – SOFEC: Start of Frame Interrupt Disable

Start of Frame Interrupt Disable

Bit 3 – EORSTEC: End of Reset Interrupt Disable

End of Reset Interrupt Disable

Bit 4 – WAKEUPEC: Wakeup Interrupt Disable

Wakeup Interrupt Disable

Bit 5 – EORSMEC: End of Resume Interrupt Disable

End of Resume Interrupt Disable

Bit 6 – UPRSMEC: Upstream Resume Interrupt Disable

Upstream Resume Interrupt Disable

Bits 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 – PEP_: Endpoint x Interrupt Disable

Endpoint x Interrupt Disable

Bits 25, 26, 27, 28, 29, 30, 31 – DMA_: DMA Channel x Interrupt Disable

DMA Channel x Interrupt Disable