MCAN Receive FIFO 1 Status
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DMS[1:0] | RF1L | F1F | |||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| F1PI[5:0] | |||||||||
| Access | R | R | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| F1GI[5:0] | |||||||||
| Access | R | R | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| F1FL[6:0] | |||||||||
| Access | R | R | R | R | R | R | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Receive FIFO 1 Fill Level
Number of elements stored in Receive FIFO 1, range 0 to 64.
Receive FIFO 1 Get Index
Receive FIFO 1 read index pointer, range 0 to 63.
Receive FIFO 1 Put Index
Receive FIFO 1 write index pointer, range 0 to 63.
Receive FIFO 1 Full
| Value | Description |
|---|---|
| 0 | Receive FIFO 1 not full. |
| 1 | Receive FIFO 1 full. |
Receive FIFO 1 Message Lost
This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset.
Overwriting the oldest message when MCAN_RXF1C.F1OM = ‘1’ will not set this flag.
| Value | Description |
|---|---|
| 0 | No Receive FIFO 1 message lost. |
| 1 | Receive FIFO 1 message lost, also set after write attempt to Receive FIFO 1 of size zero. |
Debug Message Status
| Value | Name | Description |
|---|---|---|
| 0 | IDLE | Idle state, wait for reception of debug messages, DMA request is cleared. |
| 1 | MSG_A | Debug message A received. |
| 2 | MSG_AB | Debug messages A, B received. |
| 3 | MSG_ABC | Debug messages A, B, C received, DMA request is set. |