GMAC Interrupt Status Register
This register indicates the source of the interrupt. An interrupt source must be enabled in the mask register first so the corresponding bits of this register will be set and the GMAC interrupt signal will be asserted in the system.
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TSUTIMCMP | WOL | RXLPISBC | SRI | PDRSFT | PDRQFT | ||||
| Access | R | R | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PDRSFR | PDRQFR | SFT | DRQFT | SFR | DRQFR | ||||
| Access | R | R | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PFTR | PTZ | PFNZ | HRESP | ROVR | |||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TCOMP | TFC | RLEX | TUR | TXUBR | RXUBR | RCOMP | MFS | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Management Frame Sent
The PHY Maintenance Register has completed its operation.
Cleared on read.
Receive Complete
A frame has been stored in memory.
Cleared on read.
RX Used Bit Read
Set when a receive buffer descriptor is read with its used bit set.
Cleared on read.
TX Used Bit Read
Set when a transmit buffer descriptor is read with its used bit set.
Cleared on read.
Transmit Underrun
This interrupt is set if the transmitter was forced to terminate an ongoing frame transmission due to further data being unavailable.
This interrupt is also set if a transmitter status write back has not completed when another status write back is attempted.
This interrupt is also set when the transmit DMA has written the SOP data into the FIFO and either the AHB bus was not granted in time for further data, or because an AHB not OK response was returned, or because the used bit was read.
Retry Limit Exceeded
Retry Limit Exceeded Transmit error.
Cleared on read.
Transmit Frame Corruption Due to AHB Error
Transmit frame corruption due to AHB error. Set if an error occurs during reading a transmit frame from the AHB, including HRESP errors and buffers exhausted mid frame.
Transmit Complete
Set when a frame has been transmitted.
Cleared on read.
Receive Overrun
Set when the receive overrun status bit is set.
Cleared on read.
HRESP Not OK
Set when the DMA block sees HRESP not OK.
Cleared on read.
Pause Frame with Non-zero Pause Quantum Received
Indicates a valid pause has been received that has a non-zero pause quantum field.
Cleared on read.
Pause Time Zero
Set when either the Pause Time Register at address 0x38 decrements to zero, or when a valid pause frame is received with a zero pause quantum field.
Cleared on read.
Pause Frame Transmitted
Indicates a pause frame has been successfully transmitted after being initiated from the Network Control Register.
Cleared on read.
PTP Delay Request Frame Received
Indicates a PTP delay_req frame has been received.
Cleared on read.
PTP Sync Frame Received
Indicates a PTP sync frame has been received.
Cleared on read.
PTP Delay Request Frame Transmitted
Indicates a PTP delay_req frame has been transmitted.
Cleared on read.
PTP Sync Frame Transmitted
Indicates a PTP sync frame has been transmitted.
Cleared on read.
PDelay Request Frame Received
Indicates a PTP pdelay_req frame has been received.
Cleared on read.
PDelay Response Frame Received
Indicates a PTP pdelay_resp frame has been received.
Cleared on read.
PDelay Request Frame Transmitted
Indicates a PTP pdelay_req frame has been transmitted.
Cleared on read.
PDelay Response Frame Transmitted
Indicates a PTP pdelay_resp frame has been transmitted.
Cleared on read.
TSU Seconds Register Increment
Indicates the register has incremented.
Cleared on read.
Receive LPI indication Status Bit Change
Receive LPI indication status bit change.
Cleared on read.
Wake On LAN
WOL interrupt. Indicates a WOL message has been received.
TSU Timer Comparison
Indicates when TSU timer count value is equal to programmed value.
Cleared on read.