SSC_RFMR

SSC Receive Frame Mode Register

This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register.

  0x14 32 Read/Write 0x00000000  

SSC Receive Frame Mode Register

Bit  31 30 29 28 27 26 25 24  
  FSLEN_EXT[3:0]       FSEDGE  
Access  R/W R/W R/W R/W       R/W  
Reset  0 0 0 0       0  
Bit  23 22 21 20 19 18 17 16  
    FSOS[2:0] FSLEN[3:0]  
Access    R/W R/W R/W R/W R/W R/W R/W  
Reset    0 0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
          DATNB[3:0]  
Access          R/W R/W R/W R/W  
Reset          0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  MSBF   LOOP DATLEN[4:0]  
Access  R/W   R/W R/W R/W R/W R/W R/W  
Reset  0   0 0 0 0 0 0  

Bits 4:0 – DATLEN[4:0]: Data Length

Data Length

ValueDescription
0

Forbidden value (1-bit data length not supported).

Any other value The bit stream contains DATLEN + 1 data bits.

Bit 5 – LOOP: Loop Mode

Loop Mode

ValueDescription
0

Normal operating mode.

1

RD is driven by TD, RF is driven by TF and TK drives RK.

Bit 7 – MSBF: Most Significant Bit First

Most Significant Bit First

ValueDescription
0

The lowest significant bit of the data register is sampled first in the bit stream.

1

The most significant bit of the data register is sampled first in the bit stream.

Bits 11:8 – DATNB[3:0]: Data Number per Frame

Data Number per Frame

This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1).

Bits 19:16 – FSLEN[3:0]: Receive Frame Sync Length

Receive Frame Sync Length

This field defines the number of bits sampled and stored in the Receive Sync Data Register. When this mode is selected by the START field in the Receive Clock Mode Register, it also determines the length of the sampled data to be compared to the Compare 0 or Compare 1 register.

This field is used with FSLEN_EXT to determine the pulse length of the Receive Frame Sync signal.

Pulse length is equal to FSLEN + (FSLEN_EXT × 16) + 1 Receive Clock periods.

Bits 22:20 – FSOS[2:0]: Receive Frame Sync Output Selection

Receive Frame Sync Output Selection

ValueNameDescription
0 NONE

None, RF pin is an input

1 NEGATIVE

Negative Pulse, RF pin is an output

2 POSITIVE

Positive Pulse, RF pin is an output

3 LOW

Driven Low during data transfer, RF pin is an output

4 HIGH

Driven High during data transfer, RF pin is an output

5 TOGGLING

Toggling at each start of data transfer, RF pin is an output

Bit 24 – FSEDGE: Frame Sync Edge Detection

Frame Sync Edge Detection

Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register.

ValueNameDescription
0 POSITIVE

Positive Edge Detection

1 NEGATIVE

Negative Edge Detection

Bits 31:28 – FSLEN_EXT[3:0]: FSLEN Field Extension

FSLEN Field Extension

Extends FSLEN field. For details, see FSLEN: Receive Frame Sync Length.