MLB_MIEN

MediaLB Interrupt Enable Register

  0x02C 32 Read/Write 0x00000000  
Parent topic: Register Summary

MediaLB Interrupt Enable Register

Bit  31 30 29 28 27 26 25 24  
      CTX_BREAK CTX_PE CTX_DONE CRX_BREAK CRX_PE CRX_DONE  
Access                   
Reset      0 0 0 0 0 0  
Bit  23 22 21 20 19 18 17 16  
    ATX_BREAK ATX_PE ATX_DONE ARX_BREAK ARX_PE ARX_DONE SYNC_PE  
Access                   
Reset    0 0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
                   
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
              ISOC_BUFO ISOC_PE  
Access                   
Reset              0 0  

Bit 0 – ISOC_PE: Isochronous Rx Protocol Error Enable

Isochronous Rx Protocol Error Enable

ValueDescription
1 A ProtocolError detected on an isochronous Rx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set.

Bit 1 – ISOC_BUFO: Isochronous Rx Buffer Overflow Enable

Isochronous Rx Buffer Overflow Enable

ValueDescription
1 A buffer overflow on an isochronous Rx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set. This occurs only when isochronous flow control is disabled.

Bit 16 – SYNC_PE: Synchronous Protocol Error Enable

Synchronous Protocol Error Enable

ValueDescription
1 A ProtocolError detected on a synchronous Rx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set.

Bit 17 – ARX_DONE: Asynchronous Rx Done Enable

Asynchronous Rx Done Enable

ValueDescription
1 A packet received with no errors on an asynchronous Rx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set.

Bit 18 – ARX_PE: Asynchronous Rx Protocol Error Enable

Asynchronous Rx Protocol Error Enable

ValueDescription
1 A ProtocolError detected on an asynchronous Rx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set.

Bit 19 – ARX_BREAK: Asynchronous Rx Break Enable

Asynchronous Rx Break Enable

ValueDescription
1 A AsyncBreak command received from the transmitter on an asynchronous Rx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set.

Bit 20 – ATX_DONE: Asynchronous Tx Packet Done Enable

Asynchronous Tx Packet Done Enable

Tx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set.

ValueDescription
1 A packet transmitted with no errors on an asynchronous

Bit 21 – ATX_PE: Asynchronous Tx Protocol Error Enable

Asynchronous Tx Protocol Error Enable

ValueDescription
1 A ProtocolError generated by the receiver on an asynchronous Tx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set.

Bit 22 – ATX_BREAK: Asynchronous Tx Break Enable

Asynchronous Tx Break Enable

ValueDescription
1 A ReceiverBreak response received from the receiver on an asynchronous Tx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set.

Bit 24 – CRX_DONE: Control Rx Packet Done Enable

Control Rx Packet Done Enable

ValueDescription
1 A packet received with no errors on a control Rx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set.

Bit 25 – CRX_PE: Control Rx Protocol Error Enable

Control Rx Protocol Error Enable

ValueDescription
1 A ProtocolError detected on a control Rx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set.

Bit 26 – CRX_BREAK: Control Rx Break Enable

Control Rx Break Enable

Rx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set.

ValueDescription
1 A ControlBreak command received from the transmitter on a control.

Bit 27 – CTX_DONE: Control Tx Packet Done Enable

Control Tx Packet Done Enable

ValueDescription
1 A packet transmitted with no errors on a control Tx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set.

Bit 28 – CTX_PE: Control Tx Protocol Error Enable

Control Tx Protocol Error Enable

ValueDescription
1 A ProtocolError generated by the receiver on a control Tx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set.

Bit 29 – CTX_BREAK: Control Tx Break Enable

Control Tx Break Enable

ValueDescription
1 A ReceiverBreak response received from the receiver on a control Tx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set.