AES_GHASHRx

AES GCM Intermediate Hash Word Register x

  0x78 + x*0x04 [x=0..3] 32 R/W 0x00000000   4 -1
Parent topic: Register Summary

AES GCM Intermediate Hash Word Register x

Bit  31 30 29 28 27 26 25 24  
  GHASH[31:24]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  23 22 21 20 19 18 17 16  
  GHASH[23:16]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
  GHASH[15:8]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  GHASH[7:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 31:0 – GHASH[31:0]: Intermediate GCM Hash Word x

Intermediate GCM Hash Word x

The four 32-bit Intermediate Hash Word registers expose the intermediate GHASH value. May be read to save the current GHASH value so processing can later be resumed, presumably on a later message fragment. Whenever a new key is written to the AES Key Register two automatic actions are processed:

See Key Writing and Automatic Hash Subkey Calculation for details.

If an application software-specific hash initial value is needed for the GHASH, it must be written to AES_GHASHRx: