USBHS_HSTPIP

Host Pipe Register

  0x0041C 32 Read/Write 0x00000000  
Parent topic: Register Summary

Host Pipe Register

Bit  31 30 29 28 27 26 25 24  
                PRST8  
Access                   
Reset                0  
Bit  23 22 21 20 19 18 17 16  
  PRST7 PRST6 PRST5 PRST4 PRST3 PRST2 PRST1 PRST0  
Access                   
Reset  0 0 0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
                PEN8  
Access                   
Reset                0  
Bit  7 6 5 4 3 2 1 0  
  PEN7 PEN6 PEN5 PEN4 PEN3 PEN2 PEN1 PEN0  
Access                   
Reset  0 0 0 0 0 0 0 0  

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8 – PEN: Pipe x Enable

Pipe x Enable

ValueDescription
0

Disables Pipe x, which forces the Pipe x state to inactive and resets the pipe x registers (USBHS_HSTPIPCFGx, USBHS_HSTPIPISRx, USBHS_HSTPIPIMRx), but not the pipe configuration (USBHS_HSTPIPCFGx.ALLOC, USBHS_HSTPIPCFGx.PBK, USBHS_HSTPIPCFGx.PSIZE).
1

Enables Pipe x.

Bits 16, 17, 18, 19, 20, 21, 22, 23, 24 – PRST: Pipe x Reset

Pipe x Reset

ValueDescription
0

Completes the reset operation and allows to start using the FIFO.
1

Resets the Pipe x FIFO. This resets the pipe x registers (USBHS_HSTPIPCFGx, USBHS_HSTPIPISRx, USBHS_HSTPIPIMRx), but not the pipe configuration (ALLOC, PBK, PSIZE, PTOKEN, PTYPE, PEPNUM, INTFRQ). The whole pipe mechanism (FIFO counter, reception, transmission, etc.) is reset, apart from the Data Toggle management. The pipe configuration remains active and the pipe is still enabled.