TC_FMR

TC Fault Mode Register

This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.

  0xD8 32 Read/Write 0x00000000  
Parent topic: Register Summary

TC Fault Mode Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
                   
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
              ENCF1 ENCF0  
Access              R/W R/W  
Reset              0 0  

Bit 0 – ENCF0: Enable Compare Fault Channel 0

Enable Compare Fault Channel 0

ValueDescription
0 Disables the FAULT output source (CPCS flag) from channel 0.
1 Enables the FAULT output source (CPCS flag) from channel 0.

Bit 1 – ENCF1: Enable Compare Fault Channel 1

Enable Compare Fault Channel 1

ValueDescription
0 Disables the FAULT output source (CPCS flag) from channel 1.
1 Enables the FAULT output source (CPCS flag) from channel 1.