The SUPC embeds a supply monitor located in the VDDIO power supply and which monitors VDDIO power supply.
The threshold of the supply monitor is programmable in the SMTH field of the Supply Monitor Mode register (SUPC_SMMR). Refer to the section “Electrical Characteristics”.
The supply monitor can also be enabled during one slow clock period on every one of either 32, 256 or 2048 slow clock periods, depending on the user selection. This is configured in the SUPC_SMMR.SMSMPL.
Enabling the supply monitor for such reduced times divides the typical supply monitor power consumption by factors of 2, 16 and 128, respectively, if continuous monitoring of the VDDIO power supply is not required.
A supply monitor detection generates either a reset of the core power supply or a wakeup of the core power supply. Generating a core reset when a supply monitor detection occurs is enabled by setting SUPC_SMMR.SMRSTEN.
Waking up the core power supply when a supply monitor detection occurs can be enabled by setting the SMEN bit in the Wakeup Mode register (SUPC_WUMR).
The SUPC provides two status bits in the SUPC_SR for the supply monitor that determine whether the last wakeup was due to the supply monitor:
- SUPC_SR.SMOS provides real-time information, updated at each measurement cycle or updated at each slow clock cycle, if the measurement is continuous.
- SUPC_SR.SMS provides saved information and shows a supply monitor detection has occurred since the last read of SUPC_SR.
The SMS flag generates an interrupt if SUPC_SMMR.SMIEN is set.
