Channel Initialization

The software flow required to initialize a channel must be performed in order to ensure proper operation.

For clarity, the software flow is grouped as follows:

Configure the Hardware

The MLB_MLBC0, HMCR0, HMCR1 and MLB_HCTL registers are accessible directly via APB reads and writes.

  1. 1.Initialize CTR and registers
    1. a.Clear CAT, CDT, and ADT bits in CTR
    2. b.Clear all bits of all registers
  2. 2.Configure the MediaLB interface
    1. a.Select MediaLB clock speed via MLB_MLBC0.MLBCLK
    2. b.Set MediaLB enable via MLB_MLBC0.MLBEN
  3. 3.Configure the HBI interface
    1. a.Set HMCR0 and HMCR1 = FFFFFFFFh to activate all channels
    2. b.Set the HBI enable bit: MLB_HCTL.EN = 1

Program the Routing Fabric Block

The CAT and CDT reside in the external CTR and are programmed indirectly via APB or I/O reads and writes to the MIF block.

  1. 1.Clear all bits of the CAT
  2. 2.Select a logical channel: N = 0–63
  3. 3.Program the CDT for channel N
    1. a.Set the 14-bit base address (BA)
    2. b.Set the 12-bit or 13-bit buffer depth (BD): BD = buffer depth in bytes - 1
      1. i.For synchronous channels: (BD + 1) = 4 x frames per sub-buffer (m) x bytes- per-frame (bpf)
      2. ii.For isochronous channels: (BD + 1) mod (BS + 1) = 0
      3. iii.For asynchronous channels: (BD + 1) ≥ max packet length (1024 for a MOST Data Packet (MDP); 1536 for a MOST Ethernet Packet (MEP))
      4. iv.For control channels: (BD + 1) ≥ max packet length (64)
    3. c.For isochronous channels, set the block size (BS): BS = block size in bytes - 1
    4. d.Clear all other bits of the CDT
  4. 4.Program the CAT for the inbound DMA
    1. a.For Tx channels (to MediaLB) HBI is the inbound DMA
    2. b.For Rx channels (from MediaLB) MediaLB is the inbound DMA
    3. c.Set the channel direction: RNW = 0
    4. d.Set the channel type: 
CT[2:0] = 010 (asynchronous), 001 (control), 011 (isochronous), or 000 (synchronous)
    5. e.Set the connection label: CL[5:0] = N
    6. f.If CT[2:0] = 000 (synchronous), set the mute bit (MT = 1)
    7. g.Set the channel enable: CE = 1
    8. h.Set all other bits of the CAT to ‘0’
  5. 5.Program the CAT for the outbound DMA
    1. a.For Tx channels (to MediaLB) MediaLB is the outbound DMA
    2. b.For Rx channels (from MediaLB) HBI is the outbound DMA
    3. c.Set the channel direction: RNW = 1
    4. d.Set the channel type: CT[2:0] = 010 (asynchronous), 001 (control), 011 (isochronous), or 000 (synchronous)
    5. e.Set the channel label: CL[5:0] = N
    6. f.If CT[2:0] = 000 (synchronous), set the mute bit (MT = 1)
    7. g.Set the channel enable: CE = 1
    8. h.Set all other bits of the CAT to ‘0’
  6. 6.Repeat steps 2–5 to initialize all logical channels

Program the AHB Block DMAs

The ADT resides in the external CTR and is programmed indirectly via APB reads and writes to the MIF.

  1. 1.Initialize all bits of the ADT to ‘0’
  2. 2.Select a logical channel: N = 0–63
  3. 3.Program the AHB block ping page for channel N
    1. a.Set the 32-bit base address (BA1)
    2. b.Set the 11-bit buffer depth (BD1): BD1 = buffer depth in bytes - 1
      1. i.For synchronous channels: (BD1 + 1) = n x frames per sub-buffer (m) x bytes-per-frame (bpf)
      2. ii.For isochronous channels: (BD1 + 1) mod (BS + 1) = 0
      3. iii.For asynchronous channels: 5 ≤ (BD1 + 1) ≤ 4096 (max packet length)
      4. iv.For control channels: 5 ≤ (BD1 + 1) ≤ 4096 (max packet length)
    3. c.For asynchronous and control Tx channels set the packet start bit (PS1) iff the page contains the start of the packet
    4. d.Clear the page done bit (DNE1)
    5. e.Clear the error bit (ERR1)
    6. f.Set the page ready bit (RDY1)
  4. 4.Program the AHB block pong page for channel N
    1. a.Set the 32-bit base address (BA2)
    2. b.Set the 11-bit buffer depth (BD2): BD2 = buffer depth in bytes - 1
      1. i.For synchronous channels: (BD2 +1) = n x frames per sub-buffer (m) x bytes-per-frame (bpf)
      2. ii.For isochronous channels: (BD2 + 1) mod (BS + 1) = 0
      3. iii.For asynchronous channels: 5 ≤ (BD2 + 1) ≤ 4096 (max packet length)
      4. iv.For control channels: 5 ≤ (BD2 + 1) ≤ 4096 (max packet length)
    3. c.For asynchronous and control Tx channels set the packet start bit (PS2) if the page contains the start of the packet
    4. d.Clear the page done bit (DNE2)
    5. e.Clear the error bit (ERR2)
    6. f.Set the page ready bit (RDY2)
  5. 5.Select Big Endian (LE = 0) or Little Endian (LE = 1)
  6. 6.Select the active page: PG = 0 (ping), PG = 1 (pong)
  7. 7.Set the channel enable (CE) bit for all active logical channels
  8. 8.Repeat steps 2–7 for all active logical channels
Note: All asynchronous and control packets must start with a PMP header. The first two bytes of the PMP header contains the Port Message Length (PML), which defines the length of the message that follows in bytes (not including PML itself). Hardware uses the PML to determine when a packet is complete. Asynchronous and control packets can also be segmented into two or more pages as well as contain multiple packets per page within system memory.

Synchronize and Unmute Synchronous Channel

The MLB_MLBC0 and MLB_MLBC1 registers are accessible directly via APB reads and writes.

  1. 1.Check that MediaLB clock is running (MLB_MLBC1.CLKM = 0)
  2. 2.If MLB_MLBC1.CLKM = 1, clear the register bit, wait one APB or I/O clock cycle and repeat step 1.
  3. 3.Poll for MediaLB lock (MLB_MLBC0.MLBLK = 1)
  4. 4.Wait four frames
  5. 5.Unmute synchronous channel(s)
Parent topic: Software Flow