Code loop optimization is enabled when the EEFC_FMR.CLOE bit is set.
When a backward jump is inserted in the code, the pipeline of the sequential optimization is broken and becomes inefficient. In this case, the loop code read optimization takes over from the sequential code read optimization to prevent the insertion of wait states. The loop code read optimization is enabled by default. In EEFC_FMR, if the bit CLOE is reset to 0 or the bit SCOD is set, these buffers are disabled and the loop code read is not optimized.
When code loop optimization is enabled, if inner loop body instructions L0 to Ln are positioned from the 128-bit Flash memory cell Mb0 to the memory cell Mp1, after recognition of a first backward branch, the first two Flash memory cells Mb0 and Mb1 targeted by this branch are cached for fast access from the processor at the next loop iteration.
Then by combining the sequential prefetch (described in the “Code Read Optimization” section) through the loop body with the fast read access to the loop entry cache, the entire loop can be iterated with no wait state.
The following figure illustrates code loop optimization.
