7.Program XDMAC_CBCx.BLEN with the number of microblocks of data.
8.Clear the following registers:
XDMAC_CNDCx
XDMAC_CDS_MSPx
XDMAC_CSUSx XDMAC_CDUSx
This indicates that the linked list is disabled and striding is disabled.
9.Enable the Block interrupt by writing a ‘1’ to XDMAC_CIEx.BIE, enable the Channel x Interrupt Enable bit by writing a ‘1’ to XDMAC_GIEx.IEx.
10.Enable channel x by writing a ‘1’ to the XDMAC_GE.ENx. XDMAC_GS.STx is set by hardware.
11.Once completed, the DMA channel sets XDMAC_CISx.BIS (End of Block Interrupt Status bit) and generates an interrupt. XDMAC_GS.STx is cleared by hardware. The software can either wait for an interrupt or poll the channel status bit.