Host Pipe x Set Register (Control, Bulk Pipes)
This register view is relevant only if PTYPE = 0x0 or 0x2 in ”Host Pipe x Configuration Register”.
For additional information, see ”Host Pipe x Status Register (Control, Bulk Pipes)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Sets the corresponding bit in USBHS_HSTPIPISRx, which may be useful for test or debug purposes.
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
NBUSYBKS | |||||||||
Access | |||||||||
Reset | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
SHORTPACKETIS | RXSTALLDIS | OVERFIS | NAKEDIS | PERRIS | TXSTPIS | TXOUTIS | RXINIS | ||
Access | |||||||||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Received IN Data Interrupt Set
Transmitted OUT Data Interrupt Set
Transmitted SETUP Interrupt Set
Pipe Error Interrupt Set
NAKed Interrupt Set
Overflow Interrupt Set
Received STALLed Interrupt Set
Short Packet Interrupt Set
Number of Busy Banks Set