MCAN_TXBCIE

MCAN Transmit Buffer Cancellation Finished Interrupt Enable

  0xE4 32 Read/Write 0x00000000  
Parent topic: Register Summary

MCAN Transmit Buffer Cancellation Finished Interrupt Enable

Bit  31 30 29 28 27 26 25 24  
  CFIE31 CFIE30 CFIE29 CFIE28 CFIE27 CFIE26 CFIE25 CFIE24  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  23 22 21 20 19 18 17 16  
  CFIE23 CFIE22 CFIE21 CFIE20 CFIE19 CFIE18 CFIE17 CFIE16  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
  CFIE15 CFIE14 CFIE13 CFIE12 CFIE11 CFIE10 CFIE9 CFIE8  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  CFIE7 CFIE6 CFIE5 CFIE4 CFIE3 CFIE2 CFIE1 CFIE0  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – CFIEx: Cancellation Finished Interrupt Enable for Transmit Buffer x

Cancellation Finished Interrupt Enable for Transmit Buffer x

Each Transmit Buffer has its own Cancellation Finished Interrupt Enable bit.

ValueDescription
0

Cancellation finished interrupt disabled.
1

Cancellation finished interrupt enabled.