Host DMA Channel x Control Register
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| BUFF_LENGTH[15:8] | |||||||||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| BUFF_LENGTH[7:0] | |||||||||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BURST_LCK | DESC_LD_IT | END_BUFFIT | END_TR_IT | END_B_EN | END_TR_EN | LDNXT_DSC | CHANN_ENB | ||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Channel Enable Command
If the LDNXT_DSC bit has been cleared by descriptor loading, the firmware has to set the corresponding CHANN_ENB bit to start the described transfer, if needed.
If the LDNXT_DSC bit is cleared, the channel is frozen and the channel registers may then be read and/or written reliably as soon as both the USBHS_HSTDMASTATUS.CHANN_ENB and the CHANN_ACT flags read as 0.
If a channel request is currently serviced when this bit is cleared, the DMA FIFO buffer is drained until it is empty, then the USBHS_HSTDMASTATUS.CHANN_ENB bit is cleared.
If the LDNXT_DSC bit is set or after it has been cleared, the currently loaded descriptor is skipped (no data transfer occurs) and the next descriptor is immediately loaded.
| Value | Description |
|---|---|
| 0 | The DMA channel is disabled and no transfer occurs upon request. This bit is also cleared by hardware when the channel source bus is disabled at the end of the buffer. |
| 1 | The USBHS_HSTDMASTATUS.CHANN_ENB bit is set, enabling DMA channel data transfer. Then, any pending request starts the transfer. This may be used to start or resume any requested transfer. |
Load Next Channel Transfer Descriptor Enable Command
If the CHANN_ENB bit is cleared, the next descriptor is loaded immediately upon transfer request.
DMA Channel Control Command Summary:
| Value LDNXT_DSC | Value CHANN_ENB | Name | Description |
| 0 | 0 | STOP_NOW | Stop now |
| 0 | 1 | RUN_AND_STOP | Run and stop at end of buffer |
| 1 | 0 | LOAD_NEXT_DESC | Load next descriptor now |
| 1 | 1 | RUN_AND_LINK | Run and link at end of buffer |
| Value | Description |
|---|---|
| 0 | No channel register is loaded after the end of the channel transfer. |
| 1 | The channel controller loads the next descriptor after the end of the current transfer, i.e., when the USBHS_HSTDMASTATUS.CHANN_ENB bit is reset. |
End of Transfer Enable Control (OUT transfers only)
When set, a BULK or INTERRUPT short packet closes the current buffer and the USBHS_HSTDMASTATUSx.END_TR_ST flag is raised.
This is intended for a USBHS non-prenegotiated USB transfer size.
| Value | Description |
|---|---|
| 0 | USB end of transfer is ignored. |
| 1 | The USBHS device can put an end to the current buffer transfer. |
End of Buffer Enable Control
This is mainly for short packet OUT validations initiated by the DMA reaching the end of buffer, but could be used for IN packet truncation (discarding of unwanted packet data) at the end of DMA buffer.
| Value | Description |
|---|---|
| 0 | DMA Buffer End has no impact on USB packet transfer. |
| 1 | The pipe can validate the packet (according to the values programmed in the USBHS_HSTPIPCFGx.AUTOSW and USBHS_HSTPIPIMRx.SHORTPACKETIE fields) at DMA Buffer End, i.e., when USBHS_HSTDMASTATUS.BUFF_COUNT reaches 0. |
End of Transfer Interrupt Enable
Use when the receive size is unknown.
| Value | Description |
|---|---|
| 0 | Completion of a USBHS device-initiated buffer transfer does not trigger any interrupt at USBHS_HSTDMASTATUSx.END_TR_ST rising. |
| 1 | An interrupt is sent after the buffer transfer is complete, if the USBHS device has ended the buffer transfer. |
End of Buffer Interrupt Enable
| Value | Description |
|---|---|
| 0 | USBHS_HSTDMASTATUSx.END_BF_ST rising does not trigger any interrupt. |
| 1 | An interrupt is generated when USBHS_HSTDMASTATUSx.BUFF_COUNT reaches zero. |
Descriptor Loaded Interrupt Enable
| Value | Description |
|---|---|
| 0 | USBHS_HSTDMASTATUSx.DESC_LDST rising does not trigger any interrupt. |
| 1 | An interrupt is generated when a descriptor has been loaded from the bus. |
Burst Lock Enable
| Value | Description |
|---|---|
| 0 | The DMA never locks the bus access. |
| 1 | USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration. |
Buffer Byte Length (Write-only)
This field determines the number of bytes to be transferred until end of buffer. The maximum channel transfer size (32 KBytes) is reached when this field is 0 (default value). If the transfer size is unknown, this field should be set to 0, but the transfer end may occur earlier under USB device control.
When this field is written, the USBHS_HSTDMASTATUSx.BUFF_COUNT field is updated with the write value.
Notes: 1. Bits [31:2] are only writable when issuing a channel Control Command other than “Stop Now”.
2. For reliability, it is highly recommended to wait for both the USBHS_HSTDMASTATUSx.CHAN_ACT and the CHAN_ENB flags to be at 0, thus ensuring the channel has been stopped before issuing a command other than “Stop Now”.