XDMAC_CSUS

XDMAC Channel x Source Microblock Stride Register [x = 0..23]

  0x80 + n*0x40 [n=0..23] 32 Read/Write 0x00000000   24 64

XDMAC Channel x Source Microblock Stride Register [x = 0..23]

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
  SUBS[23:16]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
  SUBS[15:8]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  SUBS[7:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 23:0 – SUBS[23:0]: Channel x Source Microblock Stride

Channel x Source Microblock Stride

Two’s complement microblock stride for channel x.