Device Endpoint Interrupt Enable Register (Isochronous Endpoints)
This register view is relevant only if EPTYPE = 0x1 in ”Device Endpoint x Configuration Register”.
For additional information, see ”Device Endpoint x Mask Register (Isochronous Endpoints)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Clears the corresponding bit in USBHS_DEVEPTIMRx.
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
RSTDTS | EPDISHDMAS | ||||||||
Access | |||||||||
Reset | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
FIFOCONS | KILLBKS | NBUSYBKES | ERRORTRANSES | DATAXES | MDATAES | ||||
Access | |||||||||
Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
SHORTPACKETES | CRCERRES | OVERFES | HBISOFLUSHES | HBISOINERRES | UNDERFES | RXOUTES | TXINES | ||
Access | |||||||||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Transmitted IN Data Interrupt Enable
Received OUT Data Interrupt Enable
Underflow Interrupt Enable
High Bandwidth Isochronous IN Error Interrupt Enable
High Bandwidth Isochronous IN Flush Interrupt Enable
Overflow Interrupt Enable
CRC Error Interrupt Enable
Short Packet Interrupt Enable
MData Interrupt Enable
DataX Interrupt Enable
Transaction Error Interrupt Enable
Number of Busy Banks Interrupt Enable
Kill IN Bank
FIFO Control
Endpoint Interrupts Disable HDMA Request Enable
Reset Data Toggle Enable