USBHS_DEVEPTIERx (ISOENPT)

Device Endpoint Interrupt Enable Register (Isochronous Endpoints)

This register view is relevant only if EPTYPE = 0x1 in ”Device Endpoint x Configuration Register”.

For additional information, see ”Device Endpoint x Mask Register (Isochronous Endpoints)”.

This register always reads as zero.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Clears the corresponding bit in USBHS_DEVEPTIMRx.

  0x01F0 + x*0x04 [x=0..9] 32 Read/Write 0   10 x

Device Endpoint Interrupt Enable Register (Isochronous Endpoints)

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
            RSTDTS   EPDISHDMAS  
Access                   
Reset            0   0  
Bit  15 14 13 12 11 10 9 8  
    FIFOCONS KILLBKS NBUSYBKES   ERRORTRANSES DATAXES MDATAES  
Access                   
Reset    0 0 0   0 0 0  
Bit  7 6 5 4 3 2 1 0  
  SHORTPACKETES CRCERRES OVERFES HBISOFLUSHES HBISOINERRES UNDERFES RXOUTES TXINES  
Access                   
Reset  0 0 0 0 0 0 0 0  

Bit 0 – TXINES: Transmitted IN Data Interrupt Enable

Transmitted IN Data Interrupt Enable

Bit 1 – RXOUTES: Received OUT Data Interrupt Enable

Received OUT Data Interrupt Enable

Bit 2 – UNDERFES: Underflow Interrupt Enable

Underflow Interrupt Enable

Bit 3 – HBISOINERRES: High Bandwidth Isochronous IN Error Interrupt Enable

High Bandwidth Isochronous IN Error Interrupt Enable

Bit 4 – HBISOFLUSHES: High Bandwidth Isochronous IN Flush Interrupt Enable

High Bandwidth Isochronous IN Flush Interrupt Enable

Bit 5 – OVERFES: Overflow Interrupt Enable

Overflow Interrupt Enable

Bit 6 – CRCERRES: CRC Error Interrupt Enable

CRC Error Interrupt Enable

Bit 7 – SHORTPACKETES: Short Packet Interrupt Enable

Short Packet Interrupt Enable

Bit 8 – MDATAES: MData Interrupt Enable

MData Interrupt Enable

Bit 9 – DATAXES: DataX Interrupt Enable

DataX Interrupt Enable

Bit 10 – ERRORTRANSES: Transaction Error Interrupt Enable

Transaction Error Interrupt Enable

Bit 12 – NBUSYBKES: Number of Busy Banks Interrupt Enable

Number of Busy Banks Interrupt Enable

Bit 13 – KILLBKS: Kill IN Bank

Kill IN Bank

Bit 14 – FIFOCONS: FIFO Control

FIFO Control

Bit 16 – EPDISHDMAS: Endpoint Interrupts Disable HDMA Request Enable

Endpoint Interrupts Disable HDMA Request Enable

Bit 18 – RSTDTS: Reset Data Toggle Enable

Reset Data Toggle Enable