MCAN_RXF0S

MCAN Receive FIFO 0 Status

  0xA4 32 Read-only 0x00000000  
Parent topic: Register Summary

MCAN Receive FIFO 0 Status

Bit  31 30 29 28 27 26 25 24  
              RF0L F0F  
Access              R R  
Reset              0 0  
Bit  23 22 21 20 19 18 17 16  
      F0PI[5:0]  
Access      R R R R R R  
Reset      0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
      F0GI[5:0]  
Access      R R R R R R  
Reset      0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
    F0FL[6:0]  
Access    R R R R R R R  
Reset    0 0 0 0 0 0 0  

Bits 6:0 – F0FL[6:0]: Receive FIFO 0 Fill Level

Receive FIFO 0 Fill Level

Number of elements stored in Receive FIFO 0, range 0 to 64.

Bits 13:8 – F0GI[5:0]: Receive FIFO 0 Get Index

Receive FIFO 0 Get Index

Receive FIFO 0 read index pointer, range 0 to 63.

Bits 21:16 – F0PI[5:0]: Receive FIFO 0 Put Index

Receive FIFO 0 Put Index

Receive FIFO 0 write index pointer, range 0 to 63.

Bit 24 – F0F: Receive FIFO 0 Full

Receive FIFO 0 Full

ValueDescription
0

Receive FIFO 0 not full.
1

Receive FIFO 0 full.

Bit 25 – RF0L: Receive FIFO 0 Message Lost

Receive FIFO 0 Message Lost

This bit is a copy of interrupt flag MCAN_IR.RF0L. When MCAN_IR.RF0L is reset, this bit is also reset.

Overwriting the oldest message when MCAN_RXF0C.F0OM = ‘1’ will not set this flag.

ValueDescription
0

No Receive FIFO 0 message lost
1

Receive FIFO 0 message lost, also set after write attempt to Receive FIFO 0 of size zero