UART_IDR

UART Interrupt Disable Register

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Disables the corresponding interrupt.

  0x0C 32 Write-only –  
Parent topic: Register Summary

UART Interrupt Disable Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
  CMP           TXEMPTY    
Access  W           W    
Reset  –           –    
Bit  7 6 5 4 3 2 1 0  
  PARE FRAME OVRE       TXRDY RXRDY  
Access  W W W       W W  
Reset  – – –       – –  

Bit 0 – RXRDY: Disable RXRDY Interrupt

Disable RXRDY Interrupt

Bit 1 – TXRDY: Disable TXRDY Interrupt

Disable TXRDY Interrupt

Bit 5 – OVRE: Disable Overrun Error Interrupt

Disable Overrun Error Interrupt

Bit 6 – FRAME: Disable Framing Error Interrupt

Disable Framing Error Interrupt

Bit 7 – PARE: Disable Parity Error Interrupt

Disable Parity Error Interrupt

Bit 9 – TXEMPTY: Disable TXEMPTY Interrupt

Disable TXEMPTY Interrupt

Bit 15 – CMP: Disable Comparison Interrupt

Disable Comparison Interrupt