HSMCI Mode Register
This register can only be written if the WPEN bit is cleared in the HSMCI Write Protection Mode Register.
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CLKODD | |||||||||
| Access | |||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PADV | FBYTE | WRPROOF | RDPROOF | PWSDIV[2:0] | |||||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLKDIV[7:0] | |||||||||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Clock Divider
High Speed MultiMedia Card Interface clock (MCCK or HSMCI_CK) is Master Clock (MCK) divided by 2 × CLKDIV + CLKODD + 2.
Power Saving Divider
High Speed MultiMedia Card Interface clock is divided by 2(PWSDIV) + 1 when entering Power Saving Mode.
Read Proof Enable
Enabling Read Proof allows to stop the HSMCI Clock during read access if the internal FIFO is full. This will guarantee data integrity, not bandwidth.
| Value | Description |
|---|---|
| 0 | Disables Read Proof. |
| 1 | Enables Read Proof. |
Write Proof Enable
Enabling Write Proof allows to stop the HSMCI Clock during write access if the internal FIFO is full. This will guarantee data integrity, not bandwidth.
| Value | Description |
|---|---|
| 0 | Disables Write Proof. |
| 1 | Enables Write Proof. |
Force Byte Transfer
Enabling Force Byte Transfer allow byte transfers, so that transfer of blocks with a size different from modulo 4 can be supported.
| Value | Description |
|---|---|
| 0 | Disables Force Byte Transfer. |
| 1 | Enables Force Byte Transfer. |
Padding Value
PADV may be only in manual transfer.
| Value | Description |
|---|---|
| 0 | 0x00 value is used when padding data in write transfer. |
| 1 | 0xFF value is used when padding data in write transfer. |
Clock divider is odd
This bit is the least significant bit of the clock divider and indicates the clock divider parity.