XDMAC Channel x Interrupt Enable Register [x=0..23]
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
ROIE | WBIE | RBIE | FIE | DIE | LIE | BIE | |||
Access | W | W | W | W | W | W | W | ||
Reset | – | – | – | – | – | – | – |
End of Block Interrupt Enable Bit
Value | Description |
---|---|
0 | No effect. |
1 | Enables end of block interrupt. |
End of Linked List Interrupt Enable Bit
Value | Description |
---|---|
0 | No effect. |
1 | Enables end of linked list interrupt. |
End of Disable Interrupt Enable Bit
Value | Description |
---|---|
0 | No effect. |
1 | Enables end of disable interrupt. |
End of Flush Interrupt Enable Bit
Value | Description |
---|---|
0 | No effect. |
1 | Enables end of flush interrupt. |
Read Bus Error Interrupt Enable Bit
Value | Description |
---|---|
0 | No effect. |
1 | Enables read bus error interrupt. |
Write Bus Error Interrupt Enable Bit
Value | Description |
---|---|
0 | No effect. |
1 | Enables write bus error interrupt. |
Request Overflow Error Interrupt Enable Bit
Value | Description |
---|---|
0 | No effect. |
1 | Enables request overflow error interrupt. |