I2SC_SR

I2SC Status Register

  0x08 32 Read-only 0x00000000  
Parent topic: Register Summary

I2SC Status Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
      TXURCH[1:0]          
Access      R R          
Reset      0 0          
Bit  15 14 13 12 11 10 9 8  
              RXORCH[1:0]  
Access              R R  
Reset              0 0  
Bit  7 6 5 4 3 2 1 0  
    TXUR TXRDY TXEN   RXOR RXRDY RXEN  
Access    R R R   R R R  
Reset    0 0 0   0 0 0  

Bit 0 – RXEN: Receiver Enabled

Receiver Enabled

ValueDescription
0

This bit is cleared when the receiver is disabled, following a RXDIS or SWRST request in I2SC_CR.
1

This bit is set when the receiver is enabled, following a RXEN request in I2SC_CR.

Bit 1 – RXRDY: Receive Ready

Receive Ready

ValueDescription
0

This bit is cleared when I2SC_RHR is read.
1

This bit is set when received data is present in I2SC_RHR.

Bit 2 – RXOR: Receive Overrun

Receive Overrun

ValueDescription
0

This bit is cleared when the corresponding bit in I2SC_SCR is written to ’1’.
1

This bit is set when an overrun error occurs on I2SC_RHR or when the corresponding bit in I2SC_SSR is written to ’1’.

Bit 4 – TXEN: Transmitter Enabled

Transmitter Enabled

ValueDescription
0

This bit is cleared when the transmitter is disabled, following a I2SC_CR.TXDIS or I2SC_CR.SWRST request.
1

This bit is set when the transmitter is enabled, following a I2SC_CR.TXEN request.

Bit 5 – TXRDY: Transmit Ready

Transmit Ready

ValueDescription
0

This bit is cleared when data is written to I2SC_THR.
1

This bit is set when I2SC_THR is empty and can be written with new data to be transmitted.

Bit 6 – TXUR: Transmit Underrun

Transmit Underrun

ValueDescription
0

This bit is cleared when the corresponding bit in I2SC_SCR is written to ’1’.
1

This bit is set when an underrun error occurs on I2SC_THR or when the corresponding bit in I2SC_SSR is written to ’1’.

Bits 9:8 – RXORCH[1:0]: Receive Overrun Channel

Receive Overrun Channel

This field is cleared when I2SC_SCR.RXOR is written to ’1’.

Bit i of this field is set when a receive overrun error occurred in channel i (i = 0 for first channel of the frame).

Bits 21:20 – TXURCH[1:0]: Transmit Underrun Channel

Transmit Underrun Channel

ValueDescription
0

This field is cleared when I2SC_SCR.TXUR is written to ’1’.
1

Bit i of this field is set when a transmit underrun error occurred in channel i (i = 0 for first channel of the frame).