HSMCI Command Register
This register is write-protected while CMDRDY is 0 in HSMCI_SR. If an Interrupt command is sent, this register is only writable by an interrupt response (field SPCMD). This means that the current command execution cannot be interrupted or modified.
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| BOOT_ACK | ATACS | IOSPCMD[1:0] | |||||||
| Access | |||||||||
| Reset | |||||||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TRTYP[2:0] | TRDIR | TRCMD[1:0] | |||||||
| Access | |||||||||
| Reset | |||||||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| MAXLAT | OPDCMD | SPCMD[2:0] | |||||||
| Access | |||||||||
| Reset | |||||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RSPTYP[1:0] | CMDNB[5:0] | ||||||||
| Access | |||||||||
| Reset | |||||||||
Command Number
This is the command index.
Response Type
| Value | Name | Description |
|---|---|---|
| 0 | NORESP | No response |
| 1 | 48_BIT | 48-bit response |
| 2 | 136_BIT | 136-bit response |
| 3 | R1B | R1b response type |
Special Command
| Value | Name | Description |
|---|---|---|
| 0 | STD | Not a special CMD. |
| 1 | INIT | Initialization CMD: 74 clock cycles for initialization sequence. |
| 2 | SYNC | Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. |
| 3 | CE_ATA | CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. |
| 4 | IT_CMD | Interrupt command: Corresponds to the Interrupt Mode (CMD40). |
| 5 | IT_RESP | Interrupt response: Corresponds to the Interrupt Mode (CMD40). |
| 6 | BOR | Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. |
| 7 | EBO | End Boot Operation. This command allows the host processor to terminate the boot operation mode. |
Open Drain Command
0 (PUSHPULL): Push pull command.
1 (OPENDRAIN): Open drain command.
Max Latency for Command to Response
0 (5): 5-cycle max latency.
1 (64): 64-cycle max latency.
Transfer Command
| Value | Name | Description |
|---|---|---|
| 0 | NO_DATA | No data transfer |
| 1 | START_DATA | Start data transfer |
| 2 | STOP_DATA | Stop data transfer |
| 3 | Reserved | Reserved |
Transfer Direction
0 (WRITE): Write.
1 (READ): Read.
Transfer Type
| Value | Name | Description |
|---|---|---|
| 0 | SINGLE | MMC/SD Card Single Block |
| 1 | MULTIPLE | MMC/SD Card Multiple Block |
| 2 | STREAM | MMC Stream |
| 4 | BYTE | SDIO Byte |
| 5 | BLOCK | SDIO Block |
SDIO Special Command
| Value | Name | Description |
|---|---|---|
| 0 | STD | Not an SDIO Special Command |
| 1 | SUSPEND | SDIO Suspend Command |
| 2 | RESUME | SDIO Resume Command |
ATA with Command Completion Signal
0 (NORMAL): Normal operation mode.
1 (COMPLETION): This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR).
Boot Operation Acknowledge
The master can choose to receive the boot acknowledge from the slave when a Boot Request command is issued. When set to one this field indicates that a Boot acknowledge is expected within a programmable amount of time defined with DTOMUL and DTOCYC fields located in the HSMCI_DTOR. If the acknowledge pattern is not received then an acknowledge timeout error is raised. If the acknowledge pattern is corrupted then an acknowledge pattern error is set.