PMC_PCER1

PMC Peripheral Clock Enable Register 1

This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.

  0x0100 32 Write-only    

PMC Peripheral Clock Enable Register 1

Bit  31 30 29 28 27 26 25 24  
    PID62   PID60 PID59 PID58 PID57 PID56  
Access                   
Reset    0   0 0 0 0 0  
Bit  23 22 21 20 19 18 17 16  
      PID53 PID52 PID51 PID50 PID49 PID48  
Access                   
Reset      0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
  PID47 PID46 PID45 PID44 PID43 PID42 PID41 PID40  
Access                   
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  PID39   PID37   PID35 PID34 PID33 PID32  
Access                   
Reset  0   0   0 0 0 0  

Bits 0, 1, 2, 3 – PIDx: Peripheral Clock x Enable

Peripheral Clock x Enable

ValueDescription
0 No effect.
1

The corresponding peripheral clock is enabled.

Note: “PIDx” refers to identifiers as defined in the section “Peripheral Identifiers”.

Bit 5 – PIDx: Peripheral Clock x Enable

Peripheral Clock x Enable

ValueDescription
0 No effect.
1

The corresponding peripheral clock is enabled.

Note: “PIDx” refers to identifiers as defined in the section “Peripheral Identifiers”.

Bits 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 – PIDx: Peripheral Clock x Enable

Peripheral Clock x Enable

ValueDescription
0 No effect.
1

The corresponding peripheral clock is enabled.

Note: “PIDx” refers to identifiers as defined in the section “Peripheral Identifiers”.

Bits 24, 25, 26, 27, 28 – PIDx: Peripheral Clock x Enable

Peripheral Clock x Enable

ValueDescription
0 No effect.
1

The corresponding peripheral clock is enabled.

Note: “PIDx” refers to identifiers as defined in the section “Peripheral Identifiers”.

Bit 30 – PIDx: Peripheral Clock x Enable

Peripheral Clock x Enable

ValueDescription
0 No effect.
1

The corresponding peripheral clock is enabled.

Note: “PIDx” refers to identifiers as defined in the section “Peripheral Identifiers”.