Clock Frequency, SCL |
fSCL |
— |
400 |
— |
1000 |
kHz |
Clock Pulse Width Low |
tLOW |
1200 |
— |
500 |
— |
ns |
Clock Pulse Width High |
tHIGH |
600 |
— |
400 |
— |
ns |
Input Filter Spike Suppression |
tI |
— |
100 |
— |
50 |
ns |
Clock Low to Data Out Valid |
tAA |
100 |
900 |
50 |
450 |
ns |
Bus Free Time between Stop and Start |
tBUF |
1300 |
— |
500 |
— |
ns |
Start Hold Time |
tHD.STA |
600 |
— |
250 |
— |
ns |
Start Set‑Up Time |
tSU.STA |
600 |
— |
250 |
— |
ns |
Data In Hold Time |
tHD.DAT |
0 |
— |
0 |
— |
ns |
Data In Set‑Up Time |
tSU.DAT |
100 |
— |
100 |
— |
ns |
Inputs Rise Time(2) |
tR |
— |
300 |
— |
300 |
ns |
Inputs Fall Time(2) |
tF |
— |
300 |
— |
100 |
ns |
Stop Set-Up Time |
tSU.STO |
600 |
— |
250 |
— |
ns |
Data Out Hold Time |
tDH |
50 |
— |
50 |
— |
ns |
Write Cycle Time |
tWR |
— |
5 |
— |
5 |
ms |