The descriptions of the pins are listed in Table 1.
Table 1. Pin Function Table
Name |
8‑Lead SOIC |
8‑Lead TSSOP |
8‑Pad UDFN(1) |
5-Lead SOT23 |
Function |
A0(2) |
1 |
1 |
1 |
— |
Device Address Input |
A1(2) |
2 |
2 |
2 |
— |
Device Address Input |
A2(2) |
3 |
3 |
3 |
— |
Device Address Input |
GND |
4 |
4 |
4 |
2 |
Ground |
SDA |
5 |
5 |
5 |
3 |
Serial Data |
SCL |
6 |
6 |
6 |
1 |
Serial Clock |
WP(2) |
7 |
7 |
7 |
5 |
Write-Protect |
VCC |
8 |
8 |
8 |
4 |
Device Power Supply |
Notes:
- 1.The exposed pad on this package
can be connected to GND or left floating.
- 2.If the A0, A1, A2 and WP pins are
not driven, they are internally pulled down to GND. In order to operate in a wide
variety of application environments, the pull‑down mechanism is intentionally
designed to be somewhat strong. Once these pins are biased above the CMOS input
buffer’s trip point (~0.5 x VCC), the pull‑down mechanism disengages.
Microchip recommends connecting these pins to a known state whenever
possible.