PIR5

Peripheral Interrupt Request Register 5
Notes:
  1. 1.RC2IF is read-only. User software must read RC2REG to clear RC2IF.
  2. 2.TX2IF is read-only. User software must load TX2REG to clear TX2IF. TX2IF does not indicate a completed transmission (use TMRT for this purpose instead).
  3. 3.Interrupt flag bits are set when an Interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable (GIE) bit. User software may ensure the appropriate interrupt flag bits are cleared before enabling an interrupt.
Name:
PIR5
Offset:
0x0091
Reset:
Access:
Bit76543210
CM2IFCM1IFBCL2IFSSP2IFBCL1IFSSP1IFRC2IFTX2IF
AccessR/W/HSR/W/HSR/W/HSR/W/HSR/W/HSR/W/HSRR
Reset00000000

Bit 7 – CM2IF: Comparator 2 Interrupt Flag

Comparator 2 Interrupt Flag

ValueDescription
1 Comparator 2 interrupt has occurred (must be cleared in software)
0 Comparator 2 interrupt event has not occurred

Bit 6 – CM1IF: Comparator 1 Interrupt Flag

Comparator 1 Interrupt Flag

ValueDescription
1 Comparator 2 interrupt has occurred (must be cleared in software)
0 Comparator 2 interrupt event has not occurred

Bit 5 – BCL2IF: MSSP2 Bus Collision Interrupt Flag

MSSP2 Bus Collision Interrupt Flag

ValueDescription
1 An MSSP2 Bus Collision interrupt has occurred (must be cleared in software)
0 No MSSP2 Bus Collision event was detected

Bit 4 – SSP2IF: MSSP2 Interrupt Flag

MSSP2 Interrupt Flag

ValueDescription
1 MSSP 2 interrupt has occurred (must be cleared in software)
0 MSSP2 interrupt event has not occurred

Bit 3 – BCL1IF: MSSP1 Bus Collision Interrupt Flag

MSSP1 Bus Collision Interrupt Flag

ValueDescription
1 An MSSP1 Bus Collision was detected (must be cleared in software)
0 No MSSP1 Bus Collision event was detected

Bit 2 – SSP1IF: MSSP1 Interrupt Flag

MSSP1 Interrupt Flag

ValueDescription
1 MSSP1 interrupt has occurred (must be cleared in software)
0 MSSP1 interrupt event has not occurred

Bit 1 – RC2IF: EUSART2 Receive Interrupt Flag(1)

EUSART2 Receive Interrupt Flag(1)

ValueDescription
1 The EUSART2 receive buffer (RC2REG) is not empty (contains at least one byte)
0 The EUSART2 receive buffer is empty

Bit 0 – TX2IF: EUSART2 Transmit Interrupt Flag(2)

EUSART2 Transmit Interrupt Flag(2)

ValueDescription
1 The EUSART2 transmit buffer (TX2REG) is empty
0 The EUSART2 transmit buffer is not empty