Pin Allocation Tables

Table 1. 8-Pin Allocation Table
I/O 8-Pin

PDIP

SOIC

DFN

ADC DAC Operational Amplifier Comparator ZCD Timers CCP 16-Bit

PWM

CWG CLC MSSP EUSART IOC Interrupt Basic
RA0 7 ANA0(4) OPA1IN1+

OPA1IN1-

OPA1(1)

C1IN0+ T3CKI(1)

T3G(1)

T4IN(1)

PWMIN0(1)

PWMIN1(1)

PWM2ERS(1)

CLCIN3(1) SCL2(1,3)

SCK2(1,3)

SDA2(1,3)

SDI2(1,3)

SS2(1)

CK1(1,3)

CK2(1,3)

IOCA0 ICSPDAT

ICDDAT

RA1 6 ANA1(4)

VREF+ (ADC)

DAC1REF0+

DAC2REF0+

C1IN0- CLCIN2(1) SCL1(1,3)

SCK1(1,3)

RX1(1)

DT1(1,3)

RX2(1)

DT2(1,3)

IOCA1 ICSPCLK

ICDCLK

RA2 5

ANA2(4)

DAC1REF0-

DAC2REF0-

OPA1IN0+

OPA1IN0-

ZCD1 T0CKI(1) CWG1(1) SDA1(1,3)

SDI1(1,3)

IOCA2 INT(1)
RA3 4 CLCIN0 (1) SS1(1) IOCA3 MCLR

VPP

RA4 3

ANA4(4)

C1IN1- T1G(1) IOCA4

CLKOUT

OSC2

SOSCO

RA5 2 ANA5(4)

ADACT(1)

T1CKI(1)

T2IN(1)

CCP1(1)

CCP2(1)

PWM1ERS(1) CLCIN1(1) IOCA5

CLKIN

OSC1

SOSCI

VDD 1 VDD
VSS 8 VSS
OUT(2)

ADGRDA

ADGRDB

DAC1OUT1

CMP1

CMP2

TMR0 CCP1

CCP2

PWM11

PWM12

PWM21

PWM22

CWG1A

CWG1B

CWG1C

CWG1D

CLC1OUT

CLC2OUT

CLC3OUT

CLC4OUT

SCL1

SCK1

SDA1

SDO1

SCL2

SCK2

SDA2

SDO2

TX1

DT1

CK1

TX2

DT2

CK2

Notes:
  1. 1.This is a PPS remappable input signal. The input function may be moved from the default location shown to any PORTx pin.
  2. 2.All output signals shown in this row are PPS remappable.
  3. 3.This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers.
  4. 4.This pin can be used as either a positive or negative analog input channel to the ADC.
Table 2. 14/16-Pin Allocation Table
I/O 14-Pin

PDIP

SOIC

TSSOP

16-Pin

VQFN

ADC DAC Operational Amplifier Comparator ZCD Timers CCP 16-Bit

PWM

CWG CLC MSSP EUSART IOC Interrupt Basic
RA0 13 12

ANA0(5)

OPA1IN3+

OPA1IN3-

OPA1(1)

C1IN0+

SS2(1)

IOCA0 ICSPDAT

ICDDAT

RA1 12 11

ANA1(5)

VREF+(ADC)

DAC1REF0+

DAC2REF0+

C1IN0-

C2IN0-

IOCA1 ICSPCLK

ICDCLK

RA2 11 10

ANA2(5)

DAC1REF0-

DAC2REF0-

OPA1IN2+

OPA1IN2-

ZCD1 T0CKI(1) CWG1(1) IOCA2 INT(1)
RA3 4 3 IOCA3 MCLR

VPP

RA4 3 2

ANA4(5)

T1G(1) IOCA4

CLKOUT

OSC2

SOSCO

RA5 2 1

ANA5(5)

T1CKI(1)

T2IN(1)

PWM1ERS(1) CLCIN3(1) IOCA5

CLKIN

OSC1

SOSCI

RC0 10 9

ANC0(5)

OPA1IN0+ C2IN0+ SCL1(1,3,4)

SCK1(1,3,4)

CK2(1,3) IOCC0
RC1 9 8

ANC1(5)

OPA1IN0-

C1IN1-

C2IN1-

T4IN(1)

PWM2ERS(1) CLCIN2(1) SDA1(1,3,4)

SDI1(1,3,4)

RX2(1)

DT2(1,3)

IOCC1
RC2 8 7 ANC2(5)

ADACT(1)

C1IN2-

C2IN2-

IOCC2
RC3 7 6

ANC3(5)

OPA1IN1+

OPA1IN1-

C1IN3-

C2IN3-

CCP2(1) PWMIN1(1) CLCIN0(1) SS1(1) IOCC3
RC4 6 5

ANC4(5)

T3G(1) CLCIN1(1)

SCK2(1,3,4)

SCL2(1,3,4)

CK1(1,3) IOCC4
RC5 5 4

ANC5(5)

T3CKI(1) CCP1(1) PWMIN0(1)

SDA2(1,3,4)

SDI2(1,3,4)

RX1(1)

DT1(1,3)

IOCC5
VDD 1 16 VDD
VSS 14 13 VSS
OUT(2)

ADGRDA

ADGRDB

DAC1OUT1

DAC1OUT2

OPA1OUT

CMP1

CMP2

TMR0 CCP1

CCP2

PWM11

PWM12

PWM21

PWM22

CWG1A

CWG1B

CWG1C

CWG1D

CLC1OUT

CLC2OUT

CLC3OUT

CLC4OUT

SCL1

SCK1

SDA1

SDO1

SCL2

SCK2

SDA2

SDO2

TX1

DT1

CK1

TX2

DT2

CK2

Notes:
  1. 1.This is a PPS remappable input signal. The input function may be moved from the default location shown to any PORTx pin.
  2. 2.All output signals shown in this row are PPS remappable.
  3. 3.This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers.
  4. 4.These pins can be configured for I2C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register.
  5. 5.This pin can be used as either a positive or negative analog input channel to the ADC.
Table 3. 20-Pin Allocation Table
I/O 20-Pin

PDIP

SOIC

SSOP

20-Pin

VQFN

ADC DAC Operational Amplifier Comparator ZCD Timers CCP 16-Bit

PWM

CWG CLC MSSP EUSART IOC Interrupt Basic
RA0 19 16

ANA0(5)

OPA1IN3+

OPA1IN3-

OPA1(1)

C1IN0+ IOCA0 ICSPDAT

ICDDAT

RA1 18 15

ANA1(5)

VREF+(ADC)

DAC1REF0+

DAC2REF0+

C1IN0-

C2IN0-

SS2(1)

IOCA1 ICSPCLK

ICDCLK

RA2 17 14

ANA2(5)

DAC1REF0-

DAC2REF0-

OPA1IN2+

OPA1IN2-

ZCD1 T0CKI(1) CWG1(1) CLCIN0(1) IOCA2 INT(1)
RA3 4 1 IOCA3 MCLR

VPP

RA4 3 20

ANA4(5)

T1G(1) IOCA4

CLKOUT

OSC2

SOSCO

RA5 2 19

ANA5(5)

T1CKI(1)

T2IN(1)

PWM1ERS(1) IOCA5

CLKIN

OSC1

SOSCI

RB4 13 10

ANB4(5)

OPA1IN0- CLCIN2(1) SDA1(1,3,4)

SDI1(1,3,4)

IOCB4
RB5 12 9

ANB5(5)

OPA1IN0+ CLCIN3(1)

SDA2(1,3,4)

SDI2(1,3,4)

RX1(1)

DT1(1,3)

IOCB5
RB6 11 8

ANB6(5)

SCL1(1,3,4)

SCK1(1,3,4)

IOCB6
RB7 10 7 ANB7(5)

SCL2(1,3,4)

SCK2(1,3,4)

CK1(1,3) IOCB7
RC0 16 13 ANC0(5) C2IN0+ CK2(1,3) IOCC0
RC1 15 12 ANC1(5) C1IN1-

C2IN1-

T4IN(1) PWM2ERS(1) RX2(1)

DT2(1,3)

IOCC1
RC2 14 11 ANC2(5)

ADACT(1)

C1IN2-

C2IN2-

IOCC2
RC3 7 4 ANC3(5) OPA1IN1+

OPA1IN1-

C1IN3-

C2IN3-

CCP2(1) PWMIN1(1) CLCIN1(1) IOCC3
RC4 6 3 ANC4(5) T3G(1) IOCC4
RC5 5 2 ANC5(5) T3CKI(1) CCP1(1) PWMIN0(1) IOCC5
RC6 8 5 ANC6(5) SS1(1) IOCC6
RC7 9 6 ANC7(5) IOCC7
VDD 1 18 VDD
VSS 20 17 VSS
OUT(2) ADGRDA

ADGRDB

DAC1OUT1

DAC1OUT2

OPA1OUT CMP1

CMP2

TMR0 CCP1

CCP2

PWM11

PWM12

PWM21

PWM22

CWG1A

CWG1B

CWG1C

CWG1D

CLC1OUT

CLC2OUT

CLC3OUT

CLC4OUT

SCL1

SCK1

SDA1

SDO1

SCL2

SCK2

SDA2

SDO2

TX1

DT1

CK1

TX2

DT2

CK2

Notes:
  1. 1.This is a PPS remappable input signal. The input function may be moved from the default location shown to any PORTx pin.
  2. 2.All output signals shown in this row are PPS remappable.
  3. 3.This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers.
  4. 4.These pins can be configured for I2C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register.
  5. 5.This pin can be used as either a positive or negative analog input channel to the ADC.