Computation Operation

The ADC module hardware is equipped with post-conversion computation features. These features provide post-processing functions such as digital filtering/averaging and threshold comparison. Based on computation results, the module can be configured to take additional samples or stop conversions and an interrupt may be asserted.

Figure 1. Computational Features Simplified Block Diagram
The operation of the ADC computational features is controlled by the MD bits.

The module can be operated in one of five modes:

The five modes are summarized in the following table.

Table 1. Computation Modes
Mode MD Register Clear Event Value after Cycle(1) Completion Threshold Operations Value at ADTIF Interrupt
ADACC and CNT ADACC ADCNT Retrigger Threshold Test Interrupt AOV ADFLTR ADCNT
Basic 0 ACLR = 1 Unchanged Unchanged No Every Sample If threshold=true N/A N/A count
Accumulate 1 ACLR = 1 S1 + ADACC or (S2-S1)(2) + ADACC If (ADCNT = 0xFF): ADCNT, otherwise: ADCNT+1 No Every Sample If threshold=true ADACC Overflow ADACC/2CRS count
Average 2 ACLR = 1 or ADCNT ≥ ADRPT at GO set or retrigger S1 + ADACC or (S2-S1) + ADACC If (ADCNT = 0xFF): ADCNT, otherwise: ADCNT+1 No If ADCNT ≥ ADRPT If threshold=true ADACC Overflow ADACC/2CRS count
Burst Average 3 ACLR = 1 or at GO set or retrigger Each repetition: same as Average End with sum of all samples Each repetition: same as Average End with ADCNT = ADRPT Repeat while ADCNT < ADRPT If ADCNT ≥ ADRPT If threshold=true ADACC Overflow ADACC/2CRS ADRPT
Low-pass Filter 4 ACLR = 1 S1 + ADACC-ADACC/
2CRS or (S2-S1) + ADACC-ADACC/2CRS If (ADCNT = 0xFF): ADCNT, otherwise: ADCNT+1 No If ADCNT ≥ ADRPT If threshold=true ADACC Overflow ADACC/2CRS (Filtered Value) count
Notes:
  1. 1.When DSEN = 0, Cycle means one conversion. When DSEN = 1, Cycle means two conversions.
  2. 2.S1 and S2 are abbreviations for Sample 1 and Sample 2, respectively. When DSEN = 0, S1 = ADRES; when DSEN = 1, S1 = ADPREV and S2 = ADRES.