OSCCON3

Oscillator Control Register 3
Note:
1. 1.If CSWHOLD = 0, the user may not see this bit set (NOSCR = 1). When the oscillator becomes ready, there may be a delay of one instruction cycle before NOSCR is set. The clock switch occurs in the next instruction cycle and NOSCR is cleared.
Name:
OSCCON3
Offset:
0x028F
Reset:
Access:
 Bit7 6 5 4 3 2 1 0 CSWHOLD SOSCPWR ORDY NOSCR AccessR/W/HC R/W R R Reset0 1 0 0

## Bit 7 – CSWHOLD: Clock Switch Hold Control

Clock Switch Hold Control

ValueDescription
1 Clock switch (and interrupt) will hold when the oscillator selected by NOSC is ready
0 Clock switch will proceed when the oscillator selected by NOSC is ready

## Bit 6 – SOSCPWR: Secondary Oscillator Power Mode Select

Secondary Oscillator Power Mode Select

ValueDescription
1 Secondary Oscillator operates in High Power mode
0 Secondary Oscillator operates in Low Power mode