OSCCON3

Oscillator Control Register 3
Note:
  1. 1.If CSWHOLD = 0, the user may not see this bit set (NOSCR = 1). When the oscillator becomes ready, there may be a delay of one instruction cycle before NOSCR is set. The clock switch occurs in the next instruction cycle and NOSCR is cleared.
Name:
OSCCON3
Offset:
0x028F
Reset:
Access:
Bit76543210
CSWHOLDSOSCPWRORDYNOSCR
AccessR/W/HCR/WRR
Reset0100

Bit 7 – CSWHOLD: Clock Switch Hold Control

Clock Switch Hold Control

ValueDescription
1 Clock switch (and interrupt) will hold when the oscillator selected by NOSC is ready
0 Clock switch will proceed when the oscillator selected by NOSC is ready

Bit 6 – SOSCPWR: Secondary Oscillator Power Mode Select

Secondary Oscillator Power Mode Select

ValueDescription
1 Secondary Oscillator operates in High Power mode
0 Secondary Oscillator operates in Low Power mode

Bit 4 – ORDY: Oscillator Ready (read-only)

Oscillator Ready (read-only)

ValueDescription
1 OSCCON1 = OSCCON2; the current system clock is the clock specified by NOSC
0 A clock switch is in progress

Bit 3 – NOSCR: New Oscillator is Ready (read-only)(1)

New Oscillator is Ready (read-only)(1)

ValueDescription
1 A clock switch is in progress and the oscillator selected by NOSC indicates a ‘ready’ condition
0 A clock switch is not in progress, or the NOSC-selected oscillator is not ready