OSCCON3
0
, the user may not see this bit set (NOSCR =
1
). When the oscillator becomes ready, there may be a
delay of one instruction cycle before NOSCR is set. The clock switch occurs
in the next instruction cycle and NOSCR is cleared.Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CSWHOLD | SOSCPWR | ORDY | NOSCR | ||||
AccessR/W/HC | R/W | R | R | ||||
Reset0 | 1 | 0 | 0 |
Clock Switch Hold Control
Value | Description |
---|---|
1 | Clock switch (and interrupt) will hold when the oscillator selected by NOSC is ready |
0 | Clock switch will proceed when the oscillator selected by NOSC is ready |
Secondary Oscillator Power Mode Select
Value | Description |
---|---|
1 | Secondary Oscillator operates in High Power mode |
0 | Secondary Oscillator operates in Low Power mode |
Oscillator Ready (read-only)
Value | Description |
---|---|
1 | OSCCON1 = OSCCON2; the current system clock is the clock specified by NOSC |
0 | A clock switch is in progress |