Power-Down Current (IPD)(1,2,3)

Table 1.
Standard Operating Conditions (unless otherwise stated)
Param. No. Sym. Device Characteristics Min. Typ.† Max. +85°C Max. +125°C Units Conditions
VDD Note
D200 IPD IPD Base 0.13 2 6 μA 3.0V  
D201 IPD_WDT Low-Frequency Internal Oscillator/WDT 0.55 3 7 μA 3.0V  
D202 IPD_SOSC Secondary Oscillator (SOSC) 1.2 4.6 9.2 μA 3.0V  
D203 IPD_LPBOR Low-Power Brown-out Reset (LPBOR) 0.25 2.5 7.3 μA 3.0V  
D204 IPD_FVR_BUF1 FVR Buffer 1 (ADC) 158 305 372 μA 3.0V  
D204A IPD_FVR_BUF2 FVR Buffer 2 (DAC/CMP) 40 68 77 μA 3.0V  
D205 IPD_BOR Brown-out Reset (BOR) 27 46 53 μA 3.0V  
D207 IPD_ADCA ADC - Active 0.13 2 6 μA 3.0V ADC is not converting (Note 4)
D208 IPD_CMP Comparator1 27 43 49 μA 3.0V  
D208A IPD_CMP Comparator2 27 43 49 μA 3.0V  

* These parameters are characterized but not tested.

† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

  1. 1.The peripheral current is the sum of the base IDD and the additional current consumed when this peripheral is enabled. The peripheral ∆ current can be determined by subtracting the base IDD or IPD current from this limit. Max. values will be used when calculating total current consumption.
  2. 2.The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode with all I/O pins in High-Impedance state and tied to VSS.
  3. 3.All peripheral currents listed are on a per-peripheral basis if more than one instance of a peripheral is available.
  4. 4.ADC clock source is ADCRC.